


mv260x(T)           VXWORKS REFERENCE MANUAL            mv260x(T)



NAME
     Motorola MVME2603, MVME2604


INTRODUCTION
     This manual entry provides board-specific information neces-
     sary  to  run  VxWorks.   Before using a board with VxWorks,
     verify that the board runs in the factory  configuration  by
     using  vendor-supplied ROMs and jumper settings and checking
     the RS-232 connection.

     The Motorola NexGen series of boards consists of three fami-
     lies:  MVME230x,  MVME260x,  and  MVME360x.  This BSP encom-
     passes only the MVME260x family.

     The MVME2600 board family consists of single-board computers
     based  on  the  PowerPC  603  and  604 microprocessors.  The
     series part numbers are of the form:

         MVME260p-tcmm

         where
             p   = processor type
                 3 = MPC603e
                 4 = MPC604ev
             t   = transition module required
                 1 = MVME761
                 2 = MVME712
             c   = processor clock frequency
                 0 = 167MHz
                 1 = 200MHz
             mm  = ECC DRAM size
                 21 = 16MB
                 31 = 32MB
                 41 = 64MB
                 51 = 128MB
                 61 = 256MB
                 91 = 96MB

     For example, an MVME2604-1131 denotes  a  PowerPC  604-based
     board  running  at  200MHz,  having  32MB  of  ECC DRAM, and
     requiring an MVME761 transition module.   Standard  hardware
     includes 5MB flash EEPROM (FLASH) and 256KB L2 cache.

     The BAT registers are not supported  in  the  current  cache
     management  strategy;  therefore,  they can best be used for
     non-cacheable, data-only address regions.

     It should be noted that there are two varieties  of  MVME761
     transition module.  The MVME761-001 has a conventional 3-row
     P2 adapter, whereas the MVME761-011 has a 5-row  P2  adapter
     which  requires  a  5-row  VME backplane.  The 5-row adapter



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     supports the enhanced P1284 parallel port interface as  well
     as full synchronous operation on serial ports 3 and 4.

     NOTE: The MVME712 module utilizes an AUI Ethernet  connector
     and cannot be used for 100baseTX communications.

     CAUTION: Do not connect an MVME712 module to a board requir-
     ing  an  MVME761  module or vice versa, as you are likely to
     damage the boards.


Boot ROMS
     The MVME2600 boards have two sets of flash  EEPROM  (FLASH).
     One  set  of two AMD Am29F040 FLASH is socketed (sockets XU1
     and XU2) and contains Motorola's Open Firmware or, on  later
     revisions,  Motorola's  PPC1-Bug.   The other set of E28f400
     FLASH is soldered in.  The VxWorks boot  kernel  resides  in
     the  soldered  FLASH.   See Hardware Details: ROM Considera-
     tions for information about loading  and  writing  the  boot
     kernel image to the soldered FLASH.

     These boards have non-volatile RAM;  thus,  boot  parameters
     are preserved whenever the system is powered off.

     To load  VxWorks,  and  for  more  information,  follow  the
     instructions in the Tornado User's Guide: Getting Started.


Jumpers
     The following jumpers are relevant to VxWorks configuration:

                                MVME260x

     Jumper   Function                   Description
     ______________________________________________________________
     J22      System controller          Install the jumper  across
                                         pins  2 and 3, if you wish
                                         to operate in  "automatic"
                                         system   controller   mode
                                         (factory   configuration).
                                         Install  the jumper across
                                         pins 1 and 2, if the board
                                         is  not  to  be the system
                                         controller under any  cir-
                                         cumstances.    And  remove
                                         the jumper if the board is
                                         to   be  the  system  con-
                                         troller in all cases.







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mv260x(T)           VXWORKS REFERENCE MANUAL            mv260x(T)



     J10      ROM controller             Install the jumper  across
                                         pins 2 and 3 to select the
                                         socketed  FLASH.   Install
                                         the  jumper  across pins 1
                                         and 2 to select  the  sol-
                                         dered  FLASH (factory con-
                                         figuration).
     J3       Level 2 cache controller   This jumper should  always
                                         be removed (factory confi-
                                         guration), causing the  L2
                                         cache    to   operate   in
                                         write-through mode.

     For details of jumper configuration, see the  board  diagram
     at the end of this entry and in the hardware manual.

     Note that ROM controller jumpers should  be  set  to  select
     socketed  FLASH  until  VxWorks boot code is written to sol-
     dered FLASH, after which the jumpers should be  restored  to
     the factory configuration of soldered FLASH.


FEATURES
     The following subsections list all supported and unsupported
     features, as well as any feature interaction.


Supported Features
     The following features of the MVME2600 board family are sup-
     ported:


     Feature           Description
     _______________________________________________________
     Processors        MPC603,  MPC604;  33  and  66MHz  bus
                       clock
     L2 Cache          256KB look-aside cache, write-through
                       only
     FLASH             4 or 8MB soldered (64-bit wide),  1MB
                       socketed   (16-bit  wide).   Soldered
                       used for VxWorks boot image.
     DRAM              16,  32,  64,  128,  256MB,   two-way
                       interleaved; auto-sized or fixed
     NVRAM             8KB (MK48T59/559) 8KB
     Peripherals       serial  ports  COM1  and  COM2;   two
                       sync/async   serial  ports;  8/16-bit
                       single-ended fast  SCSI-2  interface;
                       AUI   or  10baseT/100baseTX  Ethernet
                       interface
     ISA Interface     full 64KB memory and I/O space





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     PCI Interface     32-bit address, 32-bit data; complies
                       with  PCI  Local  Bus  Specification,
                       Revision 2.1
     VME Interface     32-bit address, 32-bit data  PCI  bus
                       interface;  A32/A24/A16,  D32/D16/D08
                       master and slave; programmable inter-
                       rupter  and  interrupt  handler; full
                       system controller function; two loca-
                       tion monitor/signal registers
     Miscellaneous     RESET switch


Unsupported Features
     The following board features are not supported:


     Feature           Description
     _______________________________________________________
     DRAM              ECC protection
     RTC               MK48T59/559; only  NVRAM  portion  is
                       used
     Peripherals       PS/2 keyboard port; PS/2 mouse  port;
                       PS/2      floppy      disk      port;
                       IEEE1284/printer parallel port
     ISA Interface     ISA RTC and DMA controllers
     PCI Interface     64-bit data
     VME Interface     D64(MBLT);  programmable   DMA   con-
                       troller with linked list support
     Miscellaneous     ABORT switch, 6 status LEDs


Feature Interactions
     None known.


HARDWARE DETAILS
     This section details device drivers and board hardware  ele-
     ments.


Devices
     The device drivers and libraries included with this BSP:

         `i8250Sio' - Intel 8250 UART driver (serial ports 1 and 2)
         `ppcDecTimer' - PowerPC decrementer timer driver (system clock)
         `dec21140' - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN)
         `byteNvRam' - byte-oriented generic non-volatile RAM driver
         `sl82565IntrCtl' - PIB interrupt controller driver
         `ravenMpic' - Motorola Raven MPIC interrupt controller driver
         `pciIomapLib' - PCI configuration library
         `universe' - Tundra Universe chip VME-to-PCI interface driver
         `z8530Sio' - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4)
         `ppcZ8536Timer' - Zilog Z8536 timer driver (auxiliary and timestamp clock)



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         `ncr810Lib' - NCR 53C825 SCSI controller library

     The `sl82565IntrCtl' module implements the  Winbond  W83C353
     PCI-to-ISA  Bridge  (PIB)  driver.  The module was developed
     originally for the Symphonic Laboratories SL82565 PIB  which
     has been succeeded by the Winbond device.


Memory Maps
     On-board RAM for these boards always appears at address  0x0
     locally.   Its  slave address on the VMEbus is set by regis-
     ters in the Universe ASIC.  Local RAM-to-VMEbus  mapping  is
     defined in config.h

     Dynamic   memory   sizing   is   supported.    By   default,
     LOCAL_MEM_AUTOSIZE  is  defined  so  memory is auto-sized at
     hardware  initialization  time.   If  auto-sizing   is   not
     selected,  LOCAL_MEM_SIZE  must be set to the actual size of
     DRAM memory available on the board to ensure all  memory  is
     available  and  VME addressing occurs properly.  The default
     fixed RAM  size  is  set  to  16MB  (see  LOCAL_MEM_SIZE  in
     config.h).

     There  are  two  basic  memory  mappings.  The  default  for
     Extended  VMEbus  access  is  discussed  here.  The optional
     pseudo-PReP memory model is  discussed  under  SPECIAL  CON-
     SIDERATIONS.

     Extended VME Memory Model:

     The following table describes the  address  mapping  created
     for the Extended VME A32 model from the CPU point of view:


     Start            Size                            Access to
     ___________________________________________________________________
     0x0              LOCAL_MEM_SIZE (16MB min)       DRAM
     LOCAL_MEM_SIZE   (0x10000000 - LOCAL_MEM_SIZE)   [not used]
     0x10000000       0xEA000000                      PCI MEM (max.  A32
                                                      VME space)
     0x10000000       128MB                           PCI  MEM  (default
                                                      A32 VME space)
     0xFA000000       16MB                            PCI MEM  (A24  VME
                                                      space)
     0xFB000000       64KB                            PCI MEM (VME  REG.
                                                      (A32) space)
     0xFB010000       0x00FE0000                      [not used]
     0xFBFF0000       64KB                            PCI MEM  (A16  VME
                                                      space)
     0xFC000000       256KB                           MPIC Reg space
     0xFC040000       0x00FC0000                      [not used]
     0xFD000000       16MB                            PCI MEM space
     0xFE000000       8MB                             PCI I/O space



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     0xFE800000       0x00780000                      [not used]
     0xFEF80000       128KB                           Falcon/Raven regs.
     0xFF000000       16MB                            ROM   space    (No
                                                      PCI/VME)

     In order to use the optional pseudo-PReP mapping  configura-
     tion,  simply  change  the #define EXTENDED_VME line to read
     #undef  EXTENDED_VME   in   config.h.    Remember   to   set
     LOCAL_MEM_SIZE  to the actual amount of DRAM on the board if
     auto-sizing is not selected.  Failure to  do  so  can  cause
     unpredictable results for A32 masters and slaves.

     In order to modify the Extended VME  mapping  configuration,
     make  the  necessary  changes  in  config.h  and,  possibly,
     sysLib.c.

     In config.h, #define the VME window variables.

     In sysLib.c, edit the sysPhysMemDesc[] page table to  modify
     the A32 VME window if you modify the sysBatDesc[] BAT regis-
     ter table.  The BAT registers allow mapping of up to 1GB  of
     data address space.  Although the BAT registers are not sup-
     ported in the current cache management strategy, you can use
     them  for non-cacheable, data-only address regions, like the
     VME A32 address space.

     When changing modes -- for example,  from  standard  VxWorks
     (pseudo-PREP-compliant  mapping)  to Extended VME mapping --
     all MVME2600 boards should be configured the same way.   The
     kernels  will  not  work  together  in a mixed configuration
     unless the memory and VME mappings are  compatible  for  all
     boards.


Shared Memory
     On all boards, shared memory across the backplane  can  also
     be  used  as  a  network  interface.  The name of the shared
     memory is `sm'.

     Shared memory network communications  requires  a  signaling
     method  and  a  method of mutually exclusive memory resource
     access.  Signalling can be done using  software  polling  or
     interrupts.   By  default,  mailbox  interrupts are used and
     SM_INT_TYPE is set to  SM_INT_MAILBOX_1.   To  use  polling,
     #define SM_INT_TYPE as SM_INT_NONE.

     There are master and slave windows into VME address space to
     access  the  VME mailbox registers so that each CPU can send
     and receive shared memory interrupts using single-byte mail-
     boxes.  The windows map a 4KB region in A32 space at address
     0xFB000000 + (0x1000 * CPU #) into the Universe chip  regis-
     ters.  This configuration allows one processor to generate a



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     SIG1 interrupt in another processor by accessing  the  other
     processor's mailbox register and setting the SIG1 bit.  Each
     CPU  has  a  master  window  covering  the   A32   addresses
     0xFB000000  through  0xFB00ffff  representing  CPU numbers 0
     through 15.  Each CPU's slave window  maps  the  appropriate
     address for that CPU to the Universe chip's register set.

     Shared memory  resource  mutual  exclusion  (spin  lock)  is
     implemented using test-and-set (TAS) and clear operations on
     byte-sized semaphores.  If the #define SM_TAS_TYPE is set to
     SM_TAS_SOFT,  only a software TAS routine is used.  Software
     TAS is usually good enough  for  shared  memory  networking;
     however,  VxMP  requires  the  use  of hardware TAS.  Enable
     hardware  TAS  by  setting   SM_TAS_TYPE   to   SM_TAS_HARD.
     Hardware  TAS  and  clear  operations  are  performed by the
     sysBusTas() and sysBusTasClear() routines, respectively, and
     invoke pseudo-atomic operations.

     True atomic operations are those which cannot  be  preempted
     at  the hardware level and appear on a bus as a single-cycle
     instruction.  Pseudo-atomic operations are composed of  mul-
     tiple  instruction  cycles  executed on a bus that is locked
     (owned) by the processor executing the instructions.

     The routine sysBusTas() performs  pseudo-atomic  TAS  opera-
     tions  by  disabling  interrupts  (to prevent deadlocks) and
     locking ownership of the VMEbus.  This routine waits  up  to
     10  microseconds  to lock the bus.  If bus ownership has not
     been achieved at the end of this period, the routine returns
     FALSE,  the  same  as  it would if the semaphore had already
     been set.

     VMEbus ownership is  necessary  for  a  number  of  reasons.
     First,  there  is  no  hardware support to propagate PowerPC
     atomic TAS instructions to the Universe chip.   Second,  the
     Universe chip (rev 1.0) has a bug which prevents proper gen-
     eration of read-modify-write (RMW)  cycles  on  the  VMEbus.
     Third,  these  boards  have  no support for propagating true
     atomic VME RMW cycles to local processor memory.

     To ensure proper clearing of the semaphore, use the  sysBus-
     TasClear().  This routine also disables interrupts and locks
     the VMEbus while accessing the semaphore.  It waits up to 10
     microseconds to gain bus ownership.  But, even if the bus is
     not owned after this period, the routine attempts  to  clear
     the semaphore.

     If one board uses software TAS, then all boards on a  shared
     memory backplane must use it.

     When hardware TAS is enabled, special consideration must  be
     given  to  the  overall system design and board locations in



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     the VME card rack.  If all VME boards on a backplane use the
     special  hardware  TAS  methods  utilized in this BSP, there
     should be no problems.  If  boards  with  differing  TAS/RMW
     capabilities  are used together, then either the first (mas-
     ter) board, which hosts the  shared  memory,  must  use  the
     hardware  TAS  method  utilized  in  this BSP, or the shared
     memory must reside on a separate VME global memory board.

     As an example of a hardware TAS  system  that  cannot  work,
     consider using a Motorola MVME162 as the master board and an
     MVME2603 as a slave.  The mv162  BSP  assumes  that  support
     exists for atomic TAS/RMW cycles on to and off of all boards
     in the system.  Furthermore, the local 68040 CPU can  access
     and alter its memory between VMEbus cycles.  Therefore, this
     system configuration does not work because there is  no  way
     to  ensure  atomic  access  to  a  semaphore by the MVME2603
     board.


Interrupts
     The system interrupt vector table has 256 entries.   Vectors
     for the various devices on the buses are assigned hierarchi-
     cally as follows:


            Vector#   Assigned to
            ________________________________________
            00 - 0f   ISA IRQ numbers 0 - 15
            10 - 1f   All MPIC interrupts
            20 - 23   Raven timers
            24 - 27   Raven interprocessor dispatch
               28     Raven detected internal errors
            29 - 55   [User defined]
            56 - 5f   Universe-specific interrupts
            60 - ff   [User defined]

     The specific ISA vector number assignments are:

           Vector#   Assigned to
           __________________________________________
              02     [Cascade interrupt from PIC2]
              03     COM2
              04     COM1
              09     Aux timers; serial ports 3 and 4

     Vector numbers not in the table are not used by this BSP.

     The standard ISA Intel 8259 Programmable Interrupt Controll-
     ers (PICs) assert their interrupts through the Raven MPIC as
     an  external  interrupt.   The  external  interrupt   vector
     numbers are:




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              Vector#   Assigned to
              ____________________________________
                 10     ISA PICs
                 11     Falcon-ECC error
                 12     PCI Ethernet
                 13     PCI SCSI
                 15     PCI Universe VME INT 0
                 16     PCI Universe VME INT 1
                 17     PCI Universe VME INT 2
                 18     PCI Universe VME INT 3
                 19     PCI PMC1/PMC2 INTA
                 1a     PCI PMC1/PMC2 INTB
                 1b     PCI PMC1/PMC2 INTC
                 1c     PCI PMC1/PMC2 INTD
                 1d     LM/SIG (mailbox) 0
                 1e     LM/SIG (mailbox) 1

     Vector numbers not in the table are not used by this BSP.

     The Raven Multi-Processor Interrupt Controller  (MPIC)  sets
     system  interrupt priorities and serves as controller of all
     external interrupts.   Each  of  its  16  interrupt  control
     registers,  designated IRQ0 through IRQ15, can be programmed
     with a relative priority from 15, the  highest,  to  0,  the
     lowest.   A priority of zero effectively disables the inter-
     rupt.  All but one of the  16  control  registers  has  been
     hardwired  to a particular interrupt source.  The IRQ number
     and priority assignments are as follows:


     Raven MPIC IRQ   Priority   IRQ Source
     ________________________________________________________________________
     IRQ0             8          Winbond PIB [all ISA interrupts]
     IRQ1             0          Falcon ECC Error
     IRQ2             14         Ethernet
     IRQ3             3          SCSI
     IRQ4             0          Graphics [not available]
     IRQ5             10         Universe LINT0 [all Universe/VME interrupts]
     IRQ6             0          Universe LINT1
     IRQ7             0          Universe LINT2
     IRQ8             0          Universe LINT3
     IRQ9             7          PCI PMC1/PMC2 INTA
     IRQ10            6 (13)     PCI PMC1/PMC2 INTB  (Secondary Ethernet)
     IRQ11            5 (2)      PCI PMC1/PMC2 INTC  (Secondary SCSI)
     IRQ12            4          PCI PMC1/PMC2 INTD
     IRQ13            0          LM/SIG Interrupt 0
     IRQ14            15         LM/SIG Interrupt 1 (mailbox)
     IRQ15            N/A        [Not used]

     For further details, refer to the appropriate board's refer-
     ence guide.

     There are only four PCI bus interrupts:  A,  B,  C,  and  D.



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     They  are  shared  among all PCI bus devices and do not have
     levels.  PCI bus interrupts are wired directly to  the  MPIC
     and,  therefore, have pre-assigned system vector numbers and
     interrupt levels.  The user enables one or more  PCI  inter-
     rupts  and connects vectored ISRs to the system by following
     these steps:


     1)   Identify the PCI interrupt letter(s) as required by the
          application.  Based  on  this,  identify the associated
          system interrupt level from the following tables:

                      Primary PCI Bus
                      ----------------
                      A = PMC_INT_LVL1
                      B = PMC_INT_LVL2
                      C = PMC_INT_LVL3
                      D = PMC_INT_LVL4

                      Secondary PCI Bus
                      -----------------
                      A = PMC_INT_LVL4
                      B = PMC_INT_LVL3
                      C = PMC_INT_LVL2
                      D = PMC_INT_LVL1


     2)   Define the vector for each PCI  interrupt  as  follows:
          INT_VEC_IRQ0  +  PMC_INT_LVLx where x is 1, 2, 3, or 4,
          as determined above.

     3)   In the application code, perform intConnect() for  each
          vector and its associated ISR.

     4)   Perform  sysIntEnable()  for  each  identified   system
          interrupt level.

     5)   When the application has finished,  perform  sysIntDis-
          able() for each identified level.


Serial Configuration
     The MVME2600 board family has four serial  ports.   All  are
     ISA  bus  devices.  Two, serial port 1 (COM1 or console) and
     serial port 2 (COM2), originate from the PC87308  Super  I/O
     (SIO) chip.  The SIO serial ports are functional equivalents
     to those in an Intel 8250 UART.

     The other two serial ports, Serial Ports 3 and 4, are imple-
     mented in the Zilog Z85230 ESCC chip and the Zilog Z8536 CIO
     chip (DTR and DSR lines).  They can be  configured  as  syn-
     chronous  serial  ports  but  no  support  for  this mode is



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     provided by this BSP.

     By default, all serial ports are configured as asynchronous,
     9600  baud,  with  1  start bit, 8 data bits, 1 stop bit, no
     parity, and no hardware  or  software  handshake.   Hardware
     handshake using RTS/CTS is a supported option on all ports.

     The four serial ports  on  MVME712  transition  modules  all
     utilize DB-25 female connectors and are DTE/DCE configurable
     by jumpers.  For details, consult MVME712M Transition Module
     and P2 Adapter Board User's Manual.

     The MVME761 transition module has two  DB-9  connectors  for
     COM1  and  COM2;  these  are  permanently configured as DCE.
     Serial ports 3 and  4  have  special  HD-26  connectors  and
     require Serial Interface Modules (SIMs) that come configured
     as DCE or DTE versions of EIA-232, EIA-530,  X.21  or  V.35.
     Jumpers  J2 and J3 control DCE/DTE selection for ports 3 and
     4, respectively.  Placing the jumpers  over  pins  1  and  2
     selects  DTE  configuration.  Jumpering pins 2 and 3 selects
     DCE.  These jumpers must match the type  of  SIM  installed.
     For  details, consult MVME761 Transition Module Installation
     and Use.


SCSI Configuration
     Only the SCSI-2 bus standard  is  supported.   The  MVME2600
     board  family  supports  an 8-bit SCSI bus using the MVME712
     and MVME761-001 transition modules.  It also supports a  16-
     bit  wide  SCSI  bus  if an MVME761-011 transition module is
     used and  the  #undef  of  SCSI_WIDE_ENABLE  is  changed  to
     #define in config.h.

     The MVME712 module and the attached  P2  adapter  card  have
     socketed  SCSI  terminators  that  are  removed or installed
     according to the system configuration.  For details, consult
     the  MVME712M  Transition Module and P2 Adapter Board User's
     Manual.

     The MVME761 module has an attached P2 adapter card that uses
     a  jumper  to  activate  SCSI bus termination.  For details,
     consult MVME761 Transition Module Installation and Use.


Network Configuration
     All boards have one  Ethernet  port  which  is  10baseT  and
     100baseTX  compatible.  The MVME2600 board family uses tran-
     sition modules to connect to this facility.

     The MVME712 transition module uses an AUI connector  and  is
     not  compatible  with 100baseTX.  Only MVME2600-1 boards can
     utilize 100baseTX communications.   The  MVME761  transition



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     module uses an RJ45 (twisted pair) jack and can be used with
     either 10baseT or 100baseTX.  The Ethernet driver  automati-
     cally   senses   and  configures  the  port  as  10baseT  or
     100baseTX.  The Ethernet  driver  is  compatible  with  both
     DEC21040 and DEC21140 devices.

     The Media Access Control (Ethernet) address for each port is
     obtained  from  a serial ROM contained in the DEC21140 chip.
     If the address is  not  found  in  serial  ROM,  the  driver
     attempts to read it from NVRAM.


VME Access
     VMEbus accesses can be classified as either master or slave.
     A  master access is one in which the accessing processor has
     bus mastership (it owns the bus) and is addressing resources
     on   another  VME  board  (the  slave  board).   The  master
     addresses the off-board resources through a  memory  mapping
     mechanism  which assigns portions of the local address space
     to the various  VME  address  spaces.   These  local  memory
     regions are windows onto the VMEbus.  Each window is indivi-
     dually configured with a set of base addresses  --  one  for
     the  local  bus,  the  other  for the VMEbus -- and a window
     size.

     A slave access is one in which slave  VME  processors  allow
     access  to  their  resources  from  the  various VME address
     spaces through slave windows.

     The normal VxWorks default is to  enable  the  slave  access
     windows  only  on  CPU 0, as part of the routine sysProcNum-
     Set().  Otherwise, slave accesses are normally  not  permit-
     ted.

     The default configuration maps all  local  memory  onto  VME
     A32.  There are no A24 or A16 slave windows.

     There is no support for the A64/D64 VME extensions.

     To disable any VME master or  slave  window,  just  set  the
     appropriate VME_Axx_xxx_SIZE macro (in config.h) to 0.  Only
     the macros in config.h are considered user options.   Macros
     in mv2600.h should not be changed by the user.

     There are  two  addressing  models  supported:  the  default
     Extended  VME  A32  and  one  for  the  optional pseudo-PReP
     address model.  For  more  information  on  the  pseudo-PReP
     model, see SPECIAL CONSIDERATIONS.

     The following lists the window parameters that the user  may
     change in config.h for both models:




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         #define VME_A32_MSTR_BUS  0x08000000
         #define VME_A32_MSTR_SIZE 0x08000000  /* (128MB) */
         #define VME_A24_MSTR_BUS  0x00000000
         #define VME_A24_MSTR_SIZE 0x01000000  /* (16MB) */
         #define VME_A16_MSTR_SIZE 0x00010000  /* (64KB) */

         #define VME_A32_SLV_LOCAL LOCAL_MEM_LOCAL_ADRS
         #define VME_A32_SLV_BUS   VME_A32_MSTR_BUS
         #define VME_A32_SLV_SIZE  LOCAL_MEM_SIZE


     The Extended VME A32 Memory Model provides extended  mapping
     to VME A32 space.  The A32 window size can extend to address
     more than 3.5GB on the VMEbus.

     The master window address mappings are as follows:


     VME Master
     Address Space   VME Base Address   Size    Local Base Address
     _____________________________________________________________
     A16             0x0000             64KB    0xFBFF0000
     A24             0x000000           16MB    0xFA000000
     A32             0x10000000         128MB   0x10000000
     A32 (Mailbox)   0xFB000000         4KB     0xFB000000

     The slave window address mappings are as follows:

     VME Slave
     Address Space   VME Base Address   Size    Local Base Address
     _______________________________________________________________
     A16 (none)
     A24 (none)
     A32             0x00000000         128MB   0x00000000
     A32 (Mailbox)   0xFB000000         4KB     0x00001000 (PCI bus)


PCI Access
     The 32-bit PCI bus is fully supported under  the  PCI  Local
     Bus  Specification, Revision 2.1.  The 64-bit extensions are
     not supported.  All configuration space  accesses  are  made
     with BDF (bus number, device number, function number) format
     calls in the  pciIomapLib  module.   For  more  information,
     refer to the man pages mv260x_pciXxx.

     The PCI address mappings are affected  by  the  VME  address
     model selected.  See SPECIAL CONSIDERATIONS.

     The Extended VME A32 address model  produces  the  following
     PCI address mapping:





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                      PCI I/O Space Access

     Start          Size             Access to
     _______________________________________________________
     0x00000000     8MB              PCI I/O space
     0x00000000     64KB             ISA I/O space
     0x00001000     4KB (fixed)      VME mailbox slave space

                      PCI MEM Space Access
     Start         Size             Access to
     _______________________________________________________
     0x00000000    16MB (min)       DRAM space
     0x10000000    ~3.7GB (max)     VME A32 master space
                   128MB (std)
     0x20000000    16MB (max)       VME A24 master space [1]
     0xFB000000    64KB (fixed)     VME mailbox (A32) space
     0xFBFF0000    64KB (max)       VME A16 master space
     0xFC000000    256KB (fixed)    MPIC REGS

         NOTE: [1] A24 and A32 address ranges must not overlap.


Boot Devices
     The supported boot devices are:

         sm - shared memory
         dc - Ethernet (10baseT or 100baseTX or AUI)

     Motorola's Open Firmware and PPC1-Bug can be used  to  down-
     load  and  run VxWorks.  Consult the relevant user's manuals
     for details.


Boot Methods
     The boot methods are affected by the boot parameters.  If no
     password  is specified, RSH (remote shell) protocol is used.
     If a password is specified, FTP protocol is used, or, if the
     flag is set, TFTP protocol is used.

     These protocols are used for both Ethernet and shared memory
     boot devices.


ROM Considerations
     Use the following command sequence on the  host  to  re-make
     the BSP boot ROM:

         cd target/config/mv260x
         make clean
         make bootrom_uncmp
         elfToBin <bootrom_uncmp >boot.bin
         chmod 666 boot.bin



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         cp boot.bin /tftpboot/boot.bin


     Power down the board and switch the  ROM  jumper  to  select
     socketed  FLASH.   Connect  the  Ethernet and console serial
     port cables, then power the board back up.

     Flashing the Boot ROM Using Motorola PPC1-Bug:

     At the PPC1-Bug prompt, start the system clock then  set  up
     the  network  transfer  from  a  TFTP host using `niot'.  To
     start the system clock, the set command must be  used.   The
     format  is:  set MMDDYYhhmm  where MM is month, DD is day of
     month, YY is year, hh is hour (24-hour format),  and  mm  is
     minutes.   This command starts the system clock and sets the
     current date and time.


        PPC1-Bug>set 1016971302


     Using `niot', the Client IP Address, Server IP Address,  and
     Gateway  IP  Address  must be set up for the user's specific
     environment:


        PPC1-Bug>niot
        Controller LUN =00?
        Device LUN     =00?
        Node Control Memory Address =00FA0000?
        Client IP Address      =123.123.10.100? 123.321.12.123
        Server IP Address      =123.123.18.105? 123.321.21.100
        Subnet IP Address Mask =255.255.255.0?
        Broadcast IP Address   =255.255.255.255?
        Gateway IP Address     =123.123.10.254? 123.321.12.254
        Boot File Name ("NULL" for None)     =? .

        Update Non-Volatile RAM (Y/N)? y
        PPC1-Bug>


     The file is transferred from the TFTP  host  to  the  target
     board  using the `niop' command.  Important: You must have a
     TFTP server running on your host's  subnet  for  the  `niop'
     command  to succeed.  The file name must be set to the loca-
     tion of the binary file on the TFTP host.  The  binary  file
     must   be  stored  in  the  directory  identified  for  TFTP
     accesses, but the file name is a relative path and does  not
     include the /tftpboot directory name:


        PPC1-Bug>niop



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        Controller LUN =00?
        Device LUN     =00?
        Get/Put        =G?
        File Name      =? boot.bin
        Memory Address =00004000?
        Length         =00000000?
        Byte Offset    =00000000?

        PPC1-Bug>


     After the file is loaded onto the target, the `pflash'  com-
     mand is used to put it into soldered FLASH parts.


        PPC1-Bug>pflash 4000:FFF00 ff000100


     When the command is  finished,  power  down  the  board  and
     switch  the ROM jumper to select soldered FLASH.  Then power
     the board back up.

     Flashing the Boot ROM Using Motorola Open Firmware:

     From the "ok" prompt on the console, use the `load'  command
     to get the image into RAM.  You must have a TFTP server run-
     ning on  your  host's  subnet  for  the  `load'  command  to
     succeed.  The command takes the following form:


         load /pci/ethernet@e:<host IP>,<file path/name>,<target IP>[,<gateway IP>]


     Note:  The modifiable parameter  load-base  is  set  to  the
     load-address  of  a  binary image to be loaded.  The factory
     preset value is 0x400000.

     For example, load-base must be modified  to  allow  for  the
     reserved  0x100  bytes  at  the  beginning of a VxWorks boot
     image:


       ok load-base h# 100 + to load-base

       ok load /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7

       Boot device: /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7
       File and args:

       ok load-base h# 100 - to load-base





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     From the "ok" prompt, determine the starting memory  address
     of soldered FLASH:


       ok 50 fal-l@
       fef80050  ff0b0006
                 ^^^


     Use the indicated first three nibbles followed by five zeros
     as the start address.  In this example, the start address is
     ff000000.  (Note: "58  fal-l@"  would  return  the  socketed
     FLASH start address.)

     From the "ok" prompt, use the gflash command to program  the
     image into FLASH.  The command takes the following form:


         <start addr> <size> <flash start addr> (gflash)


     To load the boot image into soldered FLASH, modify load-base
     as follows:


       ok load-base 100000 ff000000 (gflash)

       Erasing ...
       Programming ...
       Verifying ....
       ok


     Power down the board and switch the  ROM  jumper  to  select
     soldered FLASH.  Then power the board back up.


SPECIAL CONSIDERATIONS
     This section describes miscellaneous information  concerning
     this BSP and its use.


Delivered Objects
     The  delivered  objects   are:   `bootrom.hex',   `vxWorks',
     `vxWorks.sym', and `vxWorks.st'.


Make Targets
     The make targets are listed as the  names  of  object-format
     files.   Append  `.hex'  to each to derive a hex-format file
     name.




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     `bootrom'
     `bootrom_uncmp'
     `bootrom_res_high'  (bootrom_res does not build)
     `vxWorks' (with vxWorks.sym)
     `vxWorks_rom'
     `vxWorks.st'
     `vxWorks.st_rom'
     `vxWorks.res_rom_res_low' (vxWorks.res_rom does not build)
     `vxWorks.res_rom_nosym_res_low' (vxWorks.res_rom_nosym does not build)


Special Routines
     For these boards, the value of the CPU clock speed  is  read
     from   the   CPU  configuration  register  using  the  macro
     MEMORY_BUS_SPEED which is defined in mv2600.h.  For example:


        clkFreqMhz = MEMORY_BUS_SPEED;



VME Interrupt Vectors
     Interrupt vectors chosen to generate normal  VME  interrupts
     under  program  control must be even numbers.  VME interrupt
     service routines (ISRs) servicing VME interrupts received by
     the  Universe  chip need only be able to service even vector
     numbers.

     The Universe chip used on this board can  be  configured  to
     generate  VME  bus interrupts in response to DMA status, PCI
     bus conditions, and by specific command from software.  Dur-
     ing   the   VME  interrupt  acknowledge  (IACK)  cycle,  the
     STATUS/ID register of the Universe chip transmits  an  8-bit
     interrupt vector to the VME bus.  The seven most significant
     bits are the vector number (hence the need for  even  vector
     numbers)  and the least significant bit (LSB) is set accord-
     ing to how the Universe is configured to respond to the IACK
     cycle.   If  the interrupt was generated by software and the
     IACK cycle is received, the Universe can  be  configured  to
     send  an  acknowledging  interrupt  (SW_IACK)  back  to  the
     software over the PCI bus.   If  the  SW_IACK  interrupt  is
     enabled, the LSB is set to 0, otherwise, it is set to 1.

     The Universe chip can also  be  configured  to  receive  VME
     interrupts.   However,  the Universe is designed to mask out
     the least significant bit of the vector number  returned  by
     the  interrupting  device.  Therefore, the ISR servicing the
     VME interrupt only receives the seven most significant  bits
     of  the  vector  number from the Universe chip receiving the
     interrupt.

     Note that, if  software  specifies  an  odd  number  as  the



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     interrupt  vector  to  be transmitted during the IACK cycle,
     the STATUS/ID register will truncate it to an  even  number.
     Also,  if  any  interrupting  VME device sends an odd vector
     number, the vector number returned by the Universe to an ISR
     is  truncated  to an even vector number.  There is no confi-
     guration option  to  compensate  for  this  feature  of  the
     Universe chip.


Known Problems
     The Universe chip provides both a VME interface and  a  PCI-
     VME bridge.  The current design (rev 1.0) has numerous flaws
     that   cause   initialization   difficulties   and   prevent
     guaranteed atomic VMEbus read-modify-write (RMW) cycles.  It
     is also not capable of  receiving  more  than  one  VME  bus
     interrupt  level under conditions of frequent interrupts; it
     may lock up and prevent further VME bus interrupt  activity.
     For  further  information,  refer  to Tundra Universe Device
     Errata.

     A redesigned Universe chip (rev  1.1)  is  forthcoming  from
     Tundra  that  addresses the known flaws.  Later revisions of
     Motorola boards may utilize the new chip.

     The Motorola Raven chip has a flaw  which  ignores  PCI  bus
     `LOCK'  signals  during  access of local memory from the PCI
     bus.  Thus, an atomic RMW transaction from the Universe chip
     is  not guaranteed to be atomic in local memory.  A new chip
     (Raven 3) is forthcoming from Motorola  and  addresses  this
     flaw.

     Contact a Motorola representative for  details  on  the  new
     chips.

     Older generation VME backplanes often do  not  have  slot  1
     (the  system  controller slot) hard-wired for interrupt ack-
     nowledge (IACK) daisy chain operation, leaving  this  to  be
     done  by  a  board  plugged  in  to  the  slot.  Because the
     MVME2600 family of Motorola boards does  not  do  this,  VME
     interrupts  may not be sensed by an MVME2600 board used as a
     system controller in an old VME backplane.   New  VME  back-
     planes  usually  have  the left-most slot P1 connector hard-
     wired so that pin A20 (IACK) is connected to  A21  (IACKIN).
     On  old  VME  backplanes, the user must add a jumper between
     pins A20 and A21 on the wire wrap pins behind the P1 connec-
     tor of slot 1.


Pseudo-PReP Memory Model
     The following table describes the modified PowerPC Reference
     Platform  (PReP)  address  maps created for VME from the CPU
     point of view.   Tornado-compatible  mapping  deviates  only



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     slightly from the model.


     Start            Size                            Access to
     ___________________________________________________________________
     0x0              LOCAL_MEM_SIZE (16MB min)       DRAM
     LOCAL_MEM_SIZE   (0x80000000 - LOCAL_MEM_SIZE)   [Not used]
     0x80000000       8MB                             PCI I/O space
     0x80800000       0x3f800000                      [Not used]
     0xC0000000       16MB                            PCI MEM space
     0xC1000000       0x17000000                      [Not used]
     0xD8000000       128MB                           PCI MEM (max.  A32
                                                      VME space)
     0xE0000000       16MB                            PCI MEM  (A24  VME
                                                      space)
     0xE1000000       0x0EFF0000                      [Not used]
     0xEFFF0000       64KB                            PCI MEM  (A16  VME
                                                      space)
     0xF0000000       64KB                            PCI MEM (VME  REG.
                                                      (A32) space)
     0xF0010000       0x0BFF0000                      [Not used]
     0xFC000000       256KB                           MPIC Reg space
     0xFC040000       0x02F40000                      [Not used]
     0xFEF80000       128KB                           Falcon/Raven regs.
     0xFEFA0000       0x00060000                      [Not used]
     0xFF000000       16MB                            ROM   space    (No
                                                      PCI/VME)

     VME Access in the Pseudo-PReP Memory Model

     The pseudo-PReP memory model does  not  offer  much  address
     space  for  mapping  VME  master windows.  Only 128MB of A32
     space is available.  The 128MB window can be mapped anywhere
     in  VME  A32  space by setting the macro VME_A32_MSTR_BUS in
     config.h.  The full A16 and A24 master window address spaces
     are mapped into the system.

     The master window address mappings are as follows:

     VME Master
     Address Space   VME Base Address   Size    Local Base Address
     _____________________________________________________________
     A16             0x0000             64KB    0xEFFF0000
     A24             0x000000           16MB    0xE0000000
     A32             0x08000000         128MB   0xD8000000
     A32 (Mailbox)   0x40000000         4KB     0xF0000000

     The slave window address mappings are as follows:







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     VME Slave
     Address Space   VME Base Address   Size    Local Base Address
     _______________________________________________________________
     A16 (none)
     A24 (none)
     A32             0x00000000         128MB   0x00000000
     A32 (Mailbox)   0x40000000         4KB     0x00001000 (PCI bus)

     PCI Access in the Pseudo-PReP Memory Model

     The default pseudo-PReP mapping from the PCI  bus  point  of
     view is:

                      PCI I/O Space Access

     Start          Size             Access to
     _______________________________________________________
     0x00000000     8MB              PCI I/O space
     0x00000000     64KB             ISA I/O space
     0x00001000     4KB (fixed)      VME mailbox slave space

                      PCI MEM Space Access
     Start         Size              Access to
     _______________________________________________________
     0x80000000    16MB (min)        DRAM space
     0x18000000    16MB (std)        VME A32 master space
     0x20000000    16MB (max)        VME A24 master space
     0x2FFF0000    64KB (max)        VME A16 master space
     0x30000000    64KB (fixed)      VME mailbox (A32) space
     0x7C000000    256KB (fixed)     MPIC REGS


BOARD LAYOUT
     The diagram below shows flash EEPROM locations  and  jumpers
     relevant to VxWorks configuration:

     For the MVME260x boards, serial ports 1 through 4, the  Eth-
     ernet port, and the SCSI port appear on the VME P2 connector
     for use with the MVME712/MVME761 Transition Module.
















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______________________________               ______________________________
|             P1             |    MVME260x   |             P2              |
|                            ----------------                              |
| " <-- J3 (L2 Cache)         Needs MVME712   J22 (system contoller) --> U |
|                              or MVME761                                  |
|                            Transition Module                             |
|                                                                          |
|                                                                          |
|                                                                          |
|------------------------------------------------                          |
|        Mezzanine Board                        |                          |
|                                               |                          |
|            ----                               |                          |
|            ====                               |                          |
|            ==== <== VxWorks boot flash        |                          |
|            ====     (soldered)                |                          |
|            ----                               |                          |
|                                               |                          |
|                                               |                          |
|                    +----+   +----+            |                          |
| Open Firmware==> X |    | X |    |            |                          |
| or PPC1-Bug      U |    | U |    |            |     J10 (ROM ctrl) --> D |
|                  1 +----+ 2 +----+            |                          |
|                                               |                          |
|       Floppy/LED             Keyboard  Mouse  |      PMC 1               |
|______-------------____________-----____-----__|_...................._____|
         Key:
         X  vertical jumper installed
         :  vertical jumper absent
         -  horizontal jumper installed
         "  horizontal jumper absent
         0  switch off
         1  switch on
         U  three-pin vertical jumper, upper jumper installed
         D  three-pin vertical jumper, lower jumper installed
         L  three-pin horizontal jumper, left jumper installed
         R  three-pin horizontal jumper, right jumper installed


SEE ALSO
     Tornado User's Guide: Getting Started,
     Programmer's Guide: Configuration


BIBLIOGRAPHY
     Motorola MVME2600 Series Single Board Computer  Programmer's
     Reference Guide,
     MVME761 Transition Module Installation and Use,
     MVME712M Transition  Module  and  P2  Adapter  Board  User's
     Manual,
     Motorola PowerPC 603 RISC Microprocessor User's Manual,
     Motorola PowerPC 604 RISC Microprocessor User's Manual,



Rev: 30 Apr 97           Motorola NexGen                       22






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     Motorola  PowerPC  Microprocessor  Family:  The  Programming
     Environments,
     Motorola MPC2604GA Integrated Secondary  Cache  for  PowerPC
     Microprocessors (Glance) Data Sheets,
     Cirrus Logic Alpine  VGA  Family  -  CL-GD543X/4X  Technical
     Reference Manual,
     DECchip 21140 PCI  Fast  Ethernet  LAN  Controller  Hardware
     Reference Manual,
     National  Semiconductor  PC87308VUL  (Super   I/O   Enhanced
     Sidewinder Lite) PC Controller Manual,
     SGS-Thompson MK48T59/559 CMOS 8K x 8  TIMEKEEPER  SRAM  Data
     Sheet,
     SYM53Cxx (was NCR53C8xx) Family PCI-SCSI I/O Processors Pro-
     gramming Guide,
     Zilog SCC (Serial Communications Controller) User's Manual,
     Zilog  ZCIO  Counter/Timer  and  Parallel  I/O  Unit  User's
     Manual,
     Winbond W83C553 Enhanced  System  I/O  Controller  with  PCI
     Arbiter Data Book,
     Tundra Universe User Manual,
     Tundra Universe Device Errata,
     ANSI/VITA 1-1994 VME64 Specification,
     ANSI/IEEE 1014-1987 Versatile Backplane Bus: VMEbus,
     IEEE P1386 Draft 2.0 - Common Mezzanine  Card  Specification
     (CMC),
     IEEE P1386.1 Draft 2.0 - PCI  Mezzanine  Card  Specification
     (PMC),
     IEEE Standard 1284  Bidirectional  Parallel  Port  Interface
     Specification,
     Peripheral Component Interconnect (PCI) Local Bus Specifica-
     tion, Rev 2.1,
     PCI to PCI Bridge Architecture Specification 2.0,
     ANSI X3.131.1990 Small Computer System Interface-2  (SCSI-2)
     Draft Document





















Rev: 30 Apr 97           Motorola NexGen                       23



